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cy24488 quad pll clock generator with two-wire serial interface cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-09608 rev. *e revised november 26, 2013 quad pll clock generator with two-wire serial interface features three output frequencies plus reference out programmable output frequencie s through two-wire serial interface output frequencies from 4.9152 to 148.5 mhz uses an external 27 mhz crystal or 27 mhz input clock optional analog vcxo programmable output drive strength to minimize emi the equivalent without a serial port is the cy22388/89/91 16-pin tssop package 3.3 v operation with 2. 5 v output buffer option benefits meets most digital set top box, dvd recorder, and dtv application requirements multiple high performance plls allow synthesis of unrelated frequencies integration eliminates the need for external loop filter components complete vcxo solution with 120 ppm (typical pull range) applications and frequencies output clock application frequencies (mhz) clkc audio 6.144, 8.192, 11.2896, 12.288, 16.384, 16.9344, 18.432, 22.5792, 24.576, 33.8688, 36.864 ilink 24.576 hdmi 25.175, 28.322 clkd video 27, 27.027, 54, 54.054, 81 usb 12, 24, 48 video-pixel frequency 74.25/1. 001, 74.25, 148.5/1.001, 148.5 modem 4.9152, 11.0592 ilink 24.576 clke video 13.5, 27, 54, 81, 108 ethernet 25 pci 33.3333, 66.6666 processor 20, 30, 40, 50, 60, 80, 100 clkf see clkc/d/e refout or copy of clkc, clkd or clke clkg see clkc/d/e refout or copy of clkc, clkd or clke pll1 pll2 pll3 pll4 dividers & multiplexers vcxo serial interface & select logic xin/clkin xout vin sclk sdat clkc clkd clke clkf clkg logic block diagram
cy24488 document number: 001-09608 rev. *e page 2 of 21 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 general description ......................................................... 4 functional overview ........................................................ 4 default startup configuration ...................................... 4 reference input ..... .............. .............. .............. ............ 4 analog vcxo .............................................................. 4 crystal requirements .................................................. 4 output configurations ................................................. 5 programming flow ...................................................... 5 serial programming interface protocol and timing ..... 9 write operations ......................................................... 9 read operations ......................................................... 9 serial programming interface timing ........................... 11 absolute maximum conditions ..................................... 12 operating conditions ..................................................... 12 pullable crystal specifications (for vcxo applications) ................................................ 13 non-pullable crystal specifications (for non-vcxo applications) ........................................ 13 dc parameters ................................................................ 14 ac parameters ................................................................ 15 test and measurement setup ........................................ 16 voltage and timing definitions ..................................... 16 ordering information ...................................................... 17 ordering code definitions ..... .................................... 17 package drawing and dimensions ............................... 18 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 21 worldwide sales and design s upport ......... .............. 21 products .................................................................... 21 psoc? solutions ...................................................... 21 cypress developer community ................................. 21 technical support ................. .................................... 21
cy24488 document number: 001-09608 rev. *e page 3 of 21 pinouts figure 1. 16-pin tssop pinout 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 xin/clkin sclk sdat vin vdd1 vss clkc clkd clke clkf clkg vss vdd2 dnc avdd xout pin definitions pin name pin number description xin/clkin 1 crystal input (27 mhz) or external input clock (27 mhz) xout 16 crystal output clkc 7 clock output clkd 8 clock output clke 9 clock output clkf 10 clock output clkg 11 clock output sclk 2 serial interface clock input sdat 3 serial interface data v in 4 analog control input for vcxo dnc 14 do not connect. this pin must be left floating. avdd 15 core and input voltage supply v dd1 5 voltage supply for outputs clkc v dd2 13 voltage supply for outputs clkd, clke, clkf, clkg v ss 6, 12 ground
cy24488 document number: 001-09608 rev. *e page 4 of 21 general description the cy24488 generates up to three independent clock frequencies, and a buffered copy of the reference crystal frequency, from a single crystal or reference input. five clock output pins are available, whic h allows some frequencies to be driven on two or more output pins. outputs can also be individually enabled or disabled. when a clk output is individually disabled, it drives low. the analog voltage controlled crystal oscillator (vcxo) allows you to ?pull? the reference crystal to a frequency that is slightly higher or lower than nominal. this causes all output clocks to shift by an equivalent parts-per-million (ppm). the vcxo is controlled by the analog control voltage applied to the v in pin. for applications that do not requir e the vcxo functionality, it can be disabled. a serial programming interf ace (spi) permits in-system configuration of the device by writ ing to internal registers. it is used to set the output frequencies, enable and disable outputs, enable and disable the vcxo feature, and more. the spi provides volatile programming. when powered down, the device reverts to its prespi state. w hen the system is powered back up, the spi registers need to be configured again. specific configuration details are given in the following sections of this data sheet. customers may contact their cypress fae or salesperson for any frequency that is not listed in this data sheet. the data sheet can be updated with a new hex code for the requested frequency. functional overview default startup configuration the default state of the device refers to its state at power on. all output clocks are off except clkg, which outputs a copy of the 27 mhz reference clock. the serial programming interface must be used to configure the device for the desired output frequencies. because the serial programming memory is volatile, the device reverts to its default configuration when power is cycled. reference input there are three programmable reference operating modes for the cy24488 family of devices. table 1 on page 6 shows the data values that must be programmed into the device for each of the reference operating modes. the correct values are required to ensure frequency accuracy and vcxo pullability. the first mode uses an external 27 mhz pullable crystal and incorporates the internal analog vcxo. the crystal is connected between the xin/clkin and xo ut pins. refer the section crystal requirements for further details. the second mode disables the vcxo input control and uses a standard 27 mhz crystal. crystal requirements are relaxed relative to the vcxo mode. the crystal is connected between the xin/clkin and xout pins. refer the section crystal requirements . in this mode, tie the v in pin to avdd. the third mode accepts an external 27 mhz reference clock, applied to the xin/clkin pin. in this configuration, the xout pin must be unconnected. the vcxo f eature is not available; tie the v in pin to avdd. analog vcxo the vcxo feature allows you to fine tune the output frequency through a control voltage applied to the v in pin. a special pullable crystal must be used to have adequate vcxo pull range. this data sheet lists specific crystals that are qualified for use with the cy24488. specific serial programming values are also given for each crystal. the special crystal requirements are eliminated if the vcxo feature is not needed. to disable the vcxo, the v in pin must be tied high, and the appropriate register values given in the programming table must be programmed into the device. the vcxo is completely analog, so there is infinite resolution on the vcxo pull curve. the analog- to-digital converter steps that are normally associated with a digital vcxo input are not present in this device. vcxo profile figure 2 shows an example of a vc xo profile. the analog voltage input is on the x-axis an d the ppm range is on the y-axis. an increase in the vcxo input voltage results in a corresponding increase in the output frequency. this has the effect of moving the ppm from a negative to positive offset. figure 2. vcxo profile crystal requirements the crystal requirements for the cy24488 differ for the vcxo and non-vcxo modes. in all cases, the device must be programmed correctly for the specific crystal used, as indicated in table 1 on page 6 . crystals for non-vcxo mode when not using the vcxo, the v in pin must be tied high. the cy24488 uses a standard at-cut parallel resonant crystal, which is available in a variety of pa ckages. the key crystal parameter is load capacitance (c l ). the cy24488 has programmable load capacitance to match a range of crystal c l values. the specific configurations are shown in table 1 on page 6 . crystals with c l values outside this range are not recommended. pullable crystals for vcxo mode when the vcxo mode is used, the crystal requirements increase considerably to ensure the pullable range and glitch free pulling. table 1 on page 6 lists the crystals that cypress has qualified for use with the cy24488, and the corresponding programming configurations. customers wishing to use non-qualified crystals must first contact cypress technical support. -200 -150 -100 -50 0 50 100 150 200 00.511.5 22.533.5 vcxo input [v] tuning [pp m
cy24488 document number: 001-09608 rev. *e page 5 of 21 output configurations clkc, clkd, and clke are the three primary synthesized output clocks. for ea ch one, you can select from several clock frequencies, as shown in the following tables. to do this, find the desired frequency from the approp riate table, then use the serial programming interface to write the specified hexadecimal data into the specified memory addresses. in some cases, the data at a pa rticular memory address controls multiple functions, so only some of the bit values are specified. since a byte is the smallest unit of data that can be written, it is necessary to construct the full dat a byte before writing it. to do this, look in the other tables to find the correct values for the other bits in that byte. any of the remaining output clocks (clkf and clkg) can be configured to generate duplicate copies of any the three primary clocks. any of these clocks can also drive a buffered version of the reference crystal frequency. enabling and disabling output clocks all output clocks can be individually enabled or disabled. only clkg is on at power on. all other clocks are off (driven low), and their respective plls are off. when using the serial programming interface to set an output to a desired frequency, the pll lock time (ac parameters table) applies. when turning off an output, the output buffer and associated pll are turned off by different regist er addresses. as a result, it is possible to turn off an output by programming just one byte, but the pll continues to run and consume some power. so, the pll lock time does not apply when turning the output back on. the clock configuration tables also show a second off state that also turns off the pll, saving additional power. this requires programming one or two additional bytes, and the pll lock time applies. output drive strength output drive strength is configurable, with 2 bits available to set the drive strength for each output. the default value is ?10?, which is medium high. this is the recommended setting for outputs operating at 3.3 v. the recomm ended setting for 2.5 v outputs is ?11?, which must be programmed by you. table 9 on page 8 shows which bits must be chang ed, and how to integrate these bits with other control bits to create valid bytes for shifting in. you may program any output to a lo wer drive strength if emi is a problem. ?00? is the lowest drive strength, while ?11? is the highest. note that the lowest setting is very weak and is not suitable for most applications. output supply voltage the clock outputs may be operated at either 3.3 v or 2.5 v. clkc has its own power pin (v dd1 ), while all other clocks are powered by v dd2 . v dd1 and v dd2 may be operated at different voltages if desired. avdd must always be 3.3 v. the cy24488 also has internal register settings that must be configured for the actual output supply voltage. the default settings are optimized for v dd1 = v dd2 = 3.3 v. table 2 on page 6 and table 9 on page 8 show the values that need to be programmed for 2.5 v supply voltage. programming flow the device registers may be programmed in any sequence, but for convenience, a suggested pr ogramming flow is shown in figure 3 . any step in this programming sequence may be skipped if the default value is the desired value. when programming an output frequency, the new frequency is valid on that output after all of the specified data values are written to all of the specified addresses. when changing an output frequency, the output ma y transition through one or more indeterminate frequencies between the writing of the first byte and the last byte. note that some of the programming steps are not as independent as they appear in the flow diagram. in particular, addresses 48h, 53h, and 57h control both output frequencies and drive strength. because a byte is the smallest unit that may be programmed through the serial interface, you must consider both the frequency setting and the output drive strength when constructing the byte value to be written into these particular address. it is not necessary to write more than once to any address, but that one write must have all of the bits set correctly. example: configure clkc for 33 .8688 mhz and 2.5 v output. for address 48h, start with the value in table 3 on page 6 : 89h (binary 10001001). table 8 on page 8 shows that bits 7 and 6 control the drive strength, which must be ?11? (from table 9 on page 8 ). therefore, the final value is 11001001, which is c9h. this value is written once. figure 3. programming flow default output supply voltage settings if 2.5v (table 3) drive strength settings for 2.5v or emi (tables 9, 4, 6, 8) reference clk & crystal settings (table 2) clkc, d & e frequency settings (tables 4 - 6) clkf & g frequency settings (tables 7 - 8)
cy24488 document number: 001-09608 rev. *e page 6 of 21 table 1. register settings for vcxo and reference reference clock and vcxo crystal address manufacturer part number package specified c l 16h 17h clkin (external reference), vcxo off ? ? ? 89 3a crystal, vcxo off any any 10.7 pf 88 4f crystal, vcxo off any any 12 pf 88 5f crystal, vcxo off (default) any any 12.6 pf 88 67 crystal, vcxo off any any 14 pf 88 77 crystal, vcxo on kds dsx530ga 5 3.2 mm 12.6 pf 88 3a crystal, vcxo on kds dsx530ga 5 3.2 mm 10.7 pf 88 2a crystal, vcxo on river fcx-03 5 3.2 mm 12 pf 88 41 crystal, vcxo on kdk 5 3.2 mm 12 pf 88 3a crystal, vcxo on kds smd-49 12 pf 88 39 crystal, vcxo on ecliptek ecx-6277 smd-49 12 pf 88 41 table 2. register settings for output supply voltages output output supply voltages address 41h 43h clkc v dd1 = 3.3 v bf (default) ? v dd1 = 2.5 v 7f ? clkd, clke, clkf, clkg v dd2 = 3.3 v ? a0 (default) v dd2 = 2.5 v ? 90 table 3. clkc output frequencies (audio, ilink, or hdmi) frequency (mhz) application frequency error register address 0ah 0bh 0ch 0dh 0eh 0fh 48h [1] clkc off and pll off (default) ? ? ? ? 88 ? ? 44 8d clkc off ? ? ??????8d 25.175 hdmi 0 ppm 01 07 d2 26 18 72 ad 28.322 hdmi 0 ppm 10 39 e2 94 39 6a 91 6.144 (48 k 128) audio 0 ppm 17 3e d0 1c 06 64 a5 12.288 (32 k 384) audio 0 ppm 17 3e d0 1c 06 64 a9 16.384 (32 k 512) audio 0 ppm 17 3e d0 19 0e 64 81 18.432 (48 k 384) audio 0 ppm 17 3e d0 1c 06 64 89 24.576 (48 k 512) audio, ilink 0 ppm 17 3e d0 1c 06 64 b5 36.864 (48 k 768) audio 0 ppm 17 3e d0 1c 06 64 95 11.2896 (44.1 k 256) audio 0 ppm 17 3e d0 30 16 66 a5 16.9344 (44.1 k 384) audio 0 ppm 17 3e d0 30 16 66 85 22.5792 (44.1 k 512) audio 0 ppm 17 3e d0 30 16 66 a9 33.8688 (44.1 k 768) audio 0 ppm 17 3e d0 30 16 66 89 note 1. bits [7:6] control clkc drive strength. the values given in this table correspond to a drive strength setting of ?10?. see table 8 and table 9 on page 8 .
cy24488 document number: 001-09608 rev. *e page 7 of 21 table 4. clkd output frequencies (video, pixel rate, usb, modem or ilink) frequency (mhz) application frequency error register address 10h 11h 12h 50h clkd off and pll off (default) ? ? ? ? 00 8e clkd off ? ? ? ? ? 8e 12 usb 0 ppm 010830a2 24 usb 0 ppm 07 1e 30 86 48 usb 0 ppm 071e308a 4.9152 modem +38 ppm 18 21 26 a2 11.0592 modem +11 ppm 39 8f 28 a6 24.576 ilink 6 ppm 56 8e 33 82 27 (reference) video 0 ppm ? ? 02 9a 27.027 video 0 ppm 7b f2 33 86 54 (ref * 2) video 0 ppm 02 0e 30 8a 54.054 video 0 ppm 7b f2 33 8a 74.25/1.001 video pixel rate 0 ppm 59 f8 2c 96 74.25 video pixel rate 0 ppm 00 03 22 96 81 (ref * 3) video 0 ppm 00 07 30 b6 148.5/1.001 video pixel rate 0 ppm 59 f8 2c b2 148.5 video pixel rate 0 ppm 00 03 22 b2 table 5. clke output frequencies (ethernet, video, pci, processor) frequency (mhz) application frequency error register address 13h 14h 15h 53h [2] clke off and pll off (default) ? ? ? ? 00 3e clke off ? ? ? ? ? 3e 13.5 video 0 ppm 00 05 26 8e 27 (reference) video 0 ppm ? ? 02 6e 54 video 0 ppm 00 06 24 2e 81 video 0 ppm 00 07 24 de 108 video 0 ppm 00 06 24 5e 20 processor 0 ppm 07 26 24 9e 25 ethernet 0 ppm 07 17 30 ae 30 processor 0 ppm 01 08 28 ae 33.333333 pci 0 ppm 19 62 30 ae 40 processor 0 ppm 07 26 30 ae 50 processor 0 ppm 19 62 30 2e 60 processor 0 ppm 01 08 28 de 66.666666 pci 0 ppm 19 62 30 de 80 processor 0 ppm 07 26 30 de 100 processor 0 ppm 19 62 30 5e note 2. bits [1:0] control clkd drive strength. the values given in this table correspond to a drive strength setting of ?10?. see ta b l e 8 and table 9 on page 8 .
cy24488 document number: 001-09608 rev. *e page 8 of 21 table 6. clkf output clock frequency (mhz) address 55h, data value (hex) clkf off (default) 0c 27 mhz reference 18 copy of clkc copy of data from table 3 on page 6 address 48h copy of clkd copy of data from table 4 on page 7 address 50h copy of clke copy of data from table 5 on page 7 address 53h, divided by 4 [3] table 7. clkg output cloc k (default = reference out) frequency (mhz) address 57h bits [7:6] bits [5:0] clkg off 10 001100 27 mhz reference (default) drive strength (default=10). refer table 9 on page 8 011000 copy of clkc drive strength (default=10). refer ta b l e 9 bits[5:0] of address 48h. refer table 3 on page 6 copy of clkd drive strength (default=10). refer ta b l e 9 bits[5:0] of address 50h. refer table 4 on page 7 copy of clke drive strength (default=10). refer ta b l e 9 bits[7:2] of address 53h. refer table 5 on page 7 table 8. register settings for output drive strength [4] output clock drive strength bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkc bits[7:6] of 48h ds see address 48h in table 3 on page 6 clkd bits[1:0] of 53h see address 53h in table 5 on page 7 ds clke bits[7:6] of 54h ds 0 0 0 0 0 0 clkf bits[5:4] of 56h 1 1 ds 0 0 0 0 clkg bits[7:6] of 57h ds see address 57h in table 7 on page 8 table 9. drive strength (ds) values [4] ds value drive strength 3.3 v output 2.5 v output 00 very low emi adjustment emi adjustment 01 medium low emi adju stment emi adjustment 10 (default) medium high standard emi adjustment 11 high extra drive standard notes 3. bits [7:6] of address 55h are don?t care. dividing by 4 is equivalent to right shifting by 2 bits. 4. the default drive strength (ds) setting for all clocks is ?10? . all output specifications fo r 3.3 v outputs are given for thi s value. output specifications for 2.5 v outputs are given for a setting of ?11?. to change the ds settings, the se rial programming interface must be used to program in the des ired values. you may program in any 2-bit value, but certain output specificati ons are not valid for settings other than ?10? (3.3 v) or ?11? (2.5 v). see the dc p arameters and ac parameters tables for further details.
cy24488 document number: 001-09608 rev. *e page 9 of 21 serial programming interface protocol and timing the cy24488 uses pins sdat and sclk for a 2-wire serial interface that operates up to 4 00 kbit/s in read or write mode. except for the data hold time (t dh ), it is compliant to the i 2 c bus standard. the basic write protocol is: start bit; 7-bit device address (da); r/w bit; slave clock acknowledge (ack); 8-bit memory address (ma); ack; 8-bit data; ack; 8-bit data in ma+1 if desired; ack; 8-bit data in ma+2; ack; and more until stop bit. the basic serial format is shown in figure 5 on page 10 . device address the device address is a 7-bit val ue. the default serial interface address is 47h. data valid data is valid when the clock is high, and can be transitioned only when the clock is low, as shown in figure 6 on page 10 . data frame every new data frame is indicated by a start and stop sequence, as shown in figure 7 on page 11 . start sequence: start frame is indicated by sdat going low when sclk is high. every time a start signal is given, the next 8-bit data must be the device address (seven bits) and a r/w bit, followed by register address (eight bits) and register data (eight bits). stop sequence: stop frame is indicated by sdat going high when sclk is high. a stop frame frees the bus to write to another part on the same bus or writing to another random register address. acknowledge pulse during write mode the cy24488 responds with an acknowledge (ack) pulse after every eight bits. this is accomplished by pulling the sdat line low during the n*9 th clock cycle, as shown in figure 8 on page 11 (n = the number of bytes transmitted). during read mode the acknowledge pulse after the data packet is sent is generated by the master. write operations writing individual bytes a valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (sdat = 0/low). the next eight bits must contain the data word intended for storage. after the data word is received, the slave responds with another acknowledge bit (sdat = 0/low), and the master must end the write sequence with a stop condition. writing multiple bytes to write more than one byte at a time, the master does not end the write sequence with a stop condition. instead, the master can send multiple contiguous bytes of data to be stored. after each byte, the slave responds with an acknowledge bit, the same as after the first byte, and accepts data until the acknowledge bit is responded to by the stop condition. when receiving multiple bytes, the cy24488 internally in crements the register address. read operations read operations are initiated th e same way as write operations except that the r/w bi t of the slave address is set to ?1? (high). there are three basic read operations: current address read, random read, and sequential read. current address read the cy24488 has an onboard address counter that retains one more than the address of the last word access. if the last word written or read was word ?n?, then a current address read operation returns the value stored in location ?n+1?. when the cy24488 receives the slave address with the r/w bit set to a ?1?, the cy24488 issues an acknowledge and transmits the 8-bit word. the master device does not acknowledge the transfer, but does generate a stop conditi on, which causes the cy24488 to stop transmission. random read through random read operations, the master may access any memory location. to perform this type of read operation, first set the word address. send the addr ess to the cy24488 as part of a write operation. after the wo rd address is sent, the master generates a start condition following the acknowledge. this terminates the write operation before any data is stored in the address, but not before the intern al address pointer is set. next, the master reissues the control byte with the r/w byte set to ?1?. the cy24488 then issues an acknowledge and transmits the 8-bit word. the master device does not acknowledge the transfer, but does generate a st op condition, which causes the cy24488 to stop transmission. sequential read sequential read operations follow the same process as random reads except that the master i ssues an acknowledge instead of a stop condition after transmission of the first 8-bit data word. this action results in an incrementing of the internal address pointer, and subsequently output of the next 8-bit data word. by continuing to issue acknowledges instead of stop conditions, the master may serially read t he entire contents of the slave device memory. note that regi ster addresses outside of 0ah to 17h and 40h to 57h can be read fr om but are not real registers and do not contain configuration information. when the internal address pointer points to the ffh register, after the next increment, the pointer points to the 00h register.
cy24488 document number: 001-09608 rev. *e page 10 of 21 figure 4. data transfer sequence on the serial bus figure 5. data frame architecture figure 6. data valid and data transition periods scl start condition sdat stop data may address or acknowledge valid be changed condition sdat write start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 8-bit register data stop signal multiple contiguous registers slave 1 bit ack 8-bit register data (xxh) (xxh) (xxh+1) slave 1 bit ack 8-bit register data (xxh+2) slave 1 bit ack 8-bit register data (ffh) slave 1 bit ack 8-bit register data (00h) slave 1 bit ack slave 1 bit ack sdat read start signal device address 7-bit r/w = 1 1 bit 8-bit register data slave 1 bit ack slave 1 bit ack stop signal sdat read start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 7-bit device stop signal multiple contiguous registers master 1 bit ack 8-bit register data master 1 bit ack (xxh) (xxh) master 1 bit ack 8-bit register data (xxh+1) master 1 bit ack 8-bit register data (ffh) master 1 bit ack 8-bit register data (00h) master 1 bit ack master 1 bit ack current address read address +r/w=1 repeated start bit sdat sclk data valid transition to next bit clk low clk high vih vil t su t dh
cy24488 document number: 001-09608 rev. *e page 11 of 21 serial programming interface timing figure 7. start and stop frame figure 8. frame format (device address, r/w , register address, register data) sdat sclk start transition to next bit stop sdat sclk da6 da5 da0 r/w ack ra7 ra6 ra1 ra0 ack stop start ack d7 d6 d1 d0 +++ + + + table 10. serial programming interface timing specifications parameter description min max unit f sclk frequency of sclk ? 400 khz start mode time from sda low to scl low 0.6 ? ? s clk low sclk low period 1.3 ? ? s clk high sclk high period 0.6 ? ? s t su data transition to sclk high 100 ? ns t dh data hold (sclk low to data transition) 100 ? ns rise time of sclk and sdat ? 300 ns fall time of sclk and sdat ? 300 ns stop mode time from sclk high to sdat high 0.6 ? ? s stop mode to start mode 1.3 ? ? s
cy24488 document number: 001-09608 rev. *e page 12 of 21 absolute maximum conditions exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. table 11. absolute maximum conditions parameter description condition min max unit av dd /v dd1 /v dd2 core supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 +125 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? volts ul-94 flammability rating v-0 at 1/8 in. ? 10 ppm msl moisture sensitiv ity level 16-pin tssop 1 operating conditions parameter description min typ max unit av dd core operating voltage 3.0 3.3 3.6 v v dd1 /v dd2 output operating voltage 3.0 3.3 3.6 v 2.3 2.5 2.7 v t a ambient temperature ?10 ? 70 c c load maximum load capacitance ? ? 15 pf t pu power-up time for all v dd s reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms
cy24488 document number: 001-09608 rev. *e page 13 of 21 pullable crystal specifications (for vcxo applications) pullable crystal specifications for part cy2448 are as follows [5] parameter description condition min typ max unit f nom at-cut crystal parallel resonance, fundamental mode ? 27 ? mhz c lnom nominal load capacitance order crystal at one specific c lnom 0 ppm 11.4 12 12.6 pf r 1 equivalent series resistance (esr) fundamental mode (cl = series) ? ? 40 ? dl crystal drive level nominal v dd at 25c over 120 ppm pull range ? ? 300 ? w f 3sephi [6] third overtone separation from 3f nom mechanical third (high side of 3f nom ) 240 ? ? ppm f 3seplo [6] third overtone separation from 3f nom mechanical third (low side of 3f nom ) ? ? ?120 ppm non-pullable crystal specificati ons (for non-vcxo applications) non-pullable crystal specifications for part cy2448 are as follows [5] parameter description condition min typ max unit f nom at-cut crystal parallel resonance, fundamental mode ? 27 ? mhz c lnom nominal load capacitance order crystal at one specific c lnom 0 ppm 10.7 12 14.0 pf r 1 equivalent series resistance (esr) fundamental mode (cl = series) ? ? 40 ? dl crystal drive level nominal v dd at 25c ? ? 300 ? w notes 5. device operates to following specs which are guaranteed by design. 6. increased tolerance available from pull range less than 120 ppm.
cy24488 document number: 001-09608 rev. *e page 14 of 21 dc parameters the dc parameters for part cy24488 are as follows [7] parameter description conditions min typ max unit i oh [8] output high current v oh = v dd ? 0.5, v dd = 3.3 v 12 ? ? ma i ol [8] output low current v ol = 0.5, v dd = 3.3 v 12 ? ? ma i ih input high current v ih = v dd , excluding v in , xin/clkin ? 5 10 a i il input low current v il = 0 v, excluding v in , xin/clkin ? 5 10 a v ih input high voltage xin/clkin input cmos levels 0.7 av dd ??v v il input low voltage xin/clkin in put cmos levels ? ? 0.3 av dd v v vcxo v in input range 0 ? av dd v i vdd supply current v dd current ?60?ma c inxin input capacitance at xin/clkin vcxo disabled external reference ? 15 ? pf c inxtal input capacitance at crystal vcxo disabled fixed freq. oscillator ?12?pf notes 7. parameters are guaranteed by design and characterization. not 1 00% tested in production. all parameters specified with fully loaded outputs. 8. drive strength settings: ?10? for 3.3 v outputs; ?11? for 2.5 v outputs.
cy24488 document number: 001-09608 rev. *e page 15 of 21 ac parameters the ac parameters for part cy24488 are as follows [9] parameter description conditions min typ max units 1/t1 output frequency 4.9152 ? 148.5 mhz dc1 [10, 11] output duty cycle (excluding refout ? duty cycle is defined in figure 10 on page 16 . t 2 /t 1 , 50% of v dd external reference duty cycle between 40% and 60% measured at v dd /2 (clock output is ?? 125 mhz) 45 50 55 % dc2 [10, 11] output duty cycle (excluding refout ? duty cycle is defined in figure 10 . t 2 /t 1 , 50% of v dd external reference duty cycle between 40% and 60% measured at v dd /2 (clock output is ?? 125 mhz) 40 50 60 % dc refout [10, 11] output duty cycle duty cycle is defined in figure 10 . t 2 /t 1 , 50% of v dd (xin/clkin duty cycle = 45/55%) 40 50 60 % er [10] rising edge rate output clock edge rate. measured from 20% to 80% of v dd . c load = 15 pf. see figure 11 on page 16 . 0.75 1.2 ? v/ns ef [10] falling edge rate output clock edge rate. measured from 80% to 20% of v dd . c load = 15 pf. see figure 11 . 0.75 1.2 ? v/ns t 9 clock jitter period jitter; v dd1 = v dd2 = 3.3 v drive strength = ?10? ? 250 ? ps t 10 pll lock time from end of serial programming sequence to correct output frequency ? 1 5 ms f ? xo vcxo crystal pull range using non-smd-49 crystal specified in table 1 on page 6 . nominal crystal frequency input assumed (0 ppm) at 25 c and 3.3 v 110 120 ? ppm using smd-49 crystal specified in table 1 on page 6 . nominal crystal frequency input assumed (0 ppm) at 25 c and 3.3 v. 105 120 ? ppm notes 9. parameters are guaranteed by design and characterization. not 1 00% tested in production. all parameters specified with fully loaded outputs. 10. drive strength settings: ?10? for 3.3 v outputs; ?11? for 2.5 v outputs. 11. guaranteed when values in table 2 on page 6 and table 8 on page 8 are programmed to match the output supply voltage.
cy24488 document number: 001-09608 rev. *e page 16 of 21 test and measurement setup figure 9. test and measurement diagram voltage and timing definitions figure 10. duty cycle definition figure 11. er = (0.6 ?? v dd )/t 3 , ef = (0.6 ?? v dd )/t 4 dut v dds outputs c load gnd 0.1 ? f t 2 t 1 clock output 0v v dd 50% of v dd t 3 t 4 80% of v dd 20% of v dd clock output v dd 0v
cy24488 document number: 001-09608 rev. *e page 17 of 21 ordering code definitions ordering information part number type production flow pb-free CY24488ZXC 16-pin tssop commercial, 0 c to +70 c CY24488ZXCt 16-pin tssop ? tape and reel commercial, 0 c to +70 c x = blank or t blank = tube; t = tape and reel temperature grade: c = commercial pb-free package type: s = 16-pin tssop base part number company id: cy = cypress cy c 24488 x x z
cy24488 document number: 001-09608 rev. *e page 18 of 21 package drawing and dimensions figure 12. 16-pin tssop (4.40 mm body) z16.173/zz16.173 package outline, 51-85091 51-85091 *d
cy24488 document number: 001-09608 rev. *e page 19 of 21 acronyms document conventions units of measure acronym description ack acknowledge dtv digital television dvd digital video disc or digital versatile disc esr equivalent series resistance fae field application engineer hdmi high-definition multimedia interface i 2 c inter ic communications interface pci peripheral component interconnect pll phase-locked loop spi serial peripheral interface tssop thin-shrink small outline package usb universal serial bus vcxo voltage controlled crystal oscillator symbol unit of measure ? c degree celsius mhz megahertz mm millimeter ns nanosecond ppm parts-per-million % percentage pf picofarad vvolt
cy24488 document number: 001-09608 rev. *e page 20 of 21 document history page document title: cy24488, quad pll clock generator with two-wire serial interface document number: 001-09608 revision ecn orig. of change submission date description of change ** 497098 rgl see ecn new data sheet. *a 504259 rgl see ecn minor text additions change status from advance information to final *b 2621905 kvm / aesa 12/15/08 changed serial interface hold time (t dh ) from 0 ns to 100 ns. replaced i 2 c references with ?2-wire serial interface?; includes title change. updated data sheet template. *c 2761988 kvm 09/10/09 corrected output frequency limits in ac parameters table *d 3083299 cxq 11/10/10 removed c in spec under dc specifications table. removed ?? symbol from the typical column of t9 spec in ac specifications table. minor text edits. updated package diagram. included table of contents added ordering code definitions. added acronyms and units of measure. updated template. *e 4202940 cinm 11/26/2013 updated package drawing and dimensions : spec 51-85091 ? changed revision from *c to *d. updated in new template. completing sunset review.
document number: 001-09608 rev. *e revised november 26, 2013 page 21 of 21 all products and company names mentioned in this document may be the trademarks of their respective holders. cy24488 ? cypress semiconductor corporation, 2006-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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